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| Features * High-density, High-performance Fully CMOS, Electrically-erasable Complex Programmable Logic Device - 128 Macrocells - 5.0 ns Pin-to-pin Propagation Delay - Registered Operation up to 333 MHz - Enhanced Routing Resources - Optimized for 3.3V Operation - On-chip Voltage Regulator - 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V - SSTL2 and SSTL3 I/O Standards In-System Programming (ISP) Supported - ISP Using IEEE 1532 (JTAG) Interface - IEEE 1149.1 JTAG Boundary Scan Test Flexible Logic Macrocell - D/T/Latch Configurable Flip-flops - 5 Product Terms per Macrocell, Expandable up to 40 - Global and Individual Register Control Signals - Global and Individual Output Enable - Programmable Output Slew Rate with Low Output Drive - Programmable Open Collector Output Option - Maximum Logic Utilization by Burying a Register with a Combinatorial Output and Vice Versa Fully Green (RoHS Compliant) As Low As 70 A Standby Current Power Saving Option During Operation Using PD1 and PD2 Pins Programmable Pin-keeper Option on Inputs and I/Os Programmable Schmitt Trigger Input Option on Input and I/O Pins Programmable Input and I/O Pull-up Option Unused I/O Pins Can Be Configured as Ground (Optional) Available in Commercial and Industrial Temperature Ranges Available in 100-lead TQFP and 132-ball CBGA Advanced Digital CMOS Technology - 100% Tested - Completely Reprogrammable - 10,000 Program/Erase Cycles - 20-year Data Retention - 2000V ESD Protection - 200 mA Latch-up Immunity Security Fuse Feature Hot-Socketing Supported * Highperformance CPLD ATF1508RE * * * * * * * * * * * * * 3682A-PLD-10/08 Enhanced Features * * * * * * * * * Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms Outputs Can Be Configured for High or Low Drive Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell Three Global Clock Pins Fast Registered Input from Product Term Pull-up Option on TMS and TDI JTAG Pins OTF (On-the-Fly) Reconfiguration Mode DRA (Direct Reconfiguration Access) 1. Description The ATF1508RE is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel's proven electrically-erasable memory technology. With 128 logic macrocells and up to 84 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508RE's enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1508RE has up to 80 bi-directional I/O pins, four dedicated input pins, 1 internal voltage regulator supply input pin (VCCIRI), 6 I/O VCC pins (VCCIOA and VCCIOB), 8 ground pins (GND and 1 internal voltage regulator output pin (VCCIR0). Each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Figures 1-1 and 1-2 show the pin assignments for the 100-lead TQFP and 132-ball CBGA packages, respectively. 2 ATF1508RE 3682A-PLD-10/08 ATF1508RE Figure 1-1. 100-lead TQFP Top View I/O I/O I/O I/O I/O GND I/O I/O I/O VCCIRI INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIOB I/O I/O I/O I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O/PD1 I/O VCCIOA I/O/TDI I/O I/O I/O I/O I/O I/O GND VREFA / I/O I/O I/O I/O/TMS I/O I/O VCCIOA I/O I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIOB I/O I/O I/O I/O/TCK I/O I/O / VREFB GND I/O I/O I/O I/O I/O I/O I/O VCCIOB Note: VCCIRO (P39 for 100 TQFP) needs to be left floating and used for coupling (use 2.2 F/or 4.7 F X7R chip CAP and 470 pF NPO chip CAP. GND I/O I/O I/O I/O I/O I/O I/O VCCIOA I/O I/O I/O GND VCCIRO I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O 3 3682A-PLD-10/08 Figure 1-2. 132-CBGA Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A I/O VCCIRI I/GCLR I/O I/O NC VCCIOB NC GND I/O I/O I/O NC VCCIOB B I/O I/O GND I/O I/O NC NC NC I/O/TDO NC I/O I/O NC GND C I/O I/OE1 I/OE2/ VCCIOB GCLK2 NC I/O I/O NC NC I/O I/O I/O I/O NC NC D I/O I/O I/O I/O I/O E I/O I/O I/O I/O I/O GND F I/O/PD1 I/O I/O I/O I/O I/O G I/O I/O I/O I/O/PD2 I/O VCCIOA H I/O/VREFA I/O I/O I/O I/O GND J I/O I/O VCCIOA I/O I/O GND K I/O GND I/O VCCIRI I/O I/O L NC I/GCLK1 NC I/O I/O/VREFB I/O M NC NC I/O I/O I/O I/O NC I/O I/O/TDI I/O/TCK I/O NC NC NC N GND NC I/O NC I/O I/O NC NC GND I/O/TMS I/O GND I/O I/O P VCCIRO I/O I/O GND I/O NC VCCIOA NC I/O I/O I/O I/O VCCIOA I/O Notes: 1. The 132-ball CBGA package is 8 x 8 x 1.2 mm in size with 0.5 mm ball spacing. 2. VCCIRO (P1 for 132 CBGA) needs to be left floating and connect to coupling CAP (use 2.2 F/or 4.7 F X7R chip CAP and 470PF or 1 nF NPO chip CAP. 4 ATF1508RE 3682A-PLD-10/08 ATF1508RE Figure 1-3. Block Diagram 10 16 10 5 3682A-PLD-10/08 Each of the 128 macrocells generates a buried feedback signal that goes to the global bus (see Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508RE allows fast, efficient generation of complex logic functions. The ATF1508RE contains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1508RE macrocell, shown in Figure 1-4, is highly flexible and capable of supporting complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. A security fuse, when programmed, protects the contents of the ATF1508RE. Two bytes (16 bits) of User Electronic Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Electronic Signature is accessible regardless of the state of the security fuse. The ATF1508RE device supports In-System Programming (ISP) via the industry-standard 4-pin JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary Scan Test. ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Figure 1-4. ATF1508RE Macrocell BURIED FEEDBACK SCHMITT TRIGGER SSTL 6 ATF1508RE 3682A-PLD-10/08 ATF1508RE 1.1 Product Terms and Select Mux Each ATF1508RE macrocell has five product terms. Each product term receives as its inputs all signals from the switch matrix and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX configuration is determined by the design compiler, which selects the optimum macrocell configuration. 1.2 OR/XOR/CASCADE Logic The ATF1508RE's logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with minimal additional delay. The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. 1.3 Flip-flop The ATF1508RE's flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product term. The flip-flop changes state on the clock's rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop's asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. 1.4 Extra Feedback The ATF1508RE macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. 1.5 I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or bi-directional pin. The output enable for each macrocell can be selected from the true or complement of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input or bi-directional pin. 7 3682A-PLD-10/08 1.6 Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. 1.7 Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one of the macrocell's product terms. The 16 foldback terms in each logic block allow generation of high fan-in sum terms or other complex logic functions with little additional delay. 2. Input and I/O Pins 2.1 Programmable Pin-keeper Option for Inputs and I/Os The ATF1508RE offers the option of individually programming each of its input or I/O pin so that pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents undriven input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Figure 2-1 shows the pin-keeper circuit for an Input Pin and Figure 2-2 shows the same for an I/O pin. The pin-keeper circuit is a weak feedback latch and has an effective resistance that is approximately 50 k. Figure 2-1. Input with Programmable Pin-keeper VCCINT 50K 8 ATF1508RE 3682A-PLD-10/08 ATF1508RE Figure 2-2. I/O with Programmable Pin-keeper VCCIO VCCINT 50K 2.2 Schmitt Trigger The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt trigger option can be used to buffer inputs with slow rise times. 2.3 Output Drive Capability Each output has a high/low drive option. The low drive option (slow slew rate) can be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed or drive strength. Outputs default to high drive strength by Atmel software and can be set to low drive strength through the slew rate option. 2.4 I/O Bank The I/O pins of the ATF1508RE are grouped into two banks, Bank A and Bank B. Bank A comprises of I/O pins for macrocells 1 to 64 (Logic Block A, B, C, and D), and it is powered by VCCIOA. Bank B comprises of I/O pins for macrocells 65 to 128 (Logic Block E, F, G, and H), and it is powered by VCCIOB. 2.5 I/O Standard The ATF1508RE supports a wide range of I/O standards which include LVTTL, LVCMOS33, LVCMOS25, LVCMOS18 and LVCMOS15. The I/O pins of the ATF1508RE can also be individually configured to support SSTL-2 (Class I) and SSTL-3 (Class I) advanced I/O standards. This and the two I/O banks, together, allow the ATF1508RE to be used for voltage level translation. 9 3682A-PLD-10/08 2.6 On-Chip Voltage Regulator The ATF1508RE CPLD device has a built-in Internal Voltage Regulator that converts an external 3.3V supply to internal 1.8V core supply. The 1.8V output of the internal voltage regulator is also connected to the VCCIRO pin (Pin 39 for 100-pin TQFP) so that external bypass capacitors can be used to minimize noise. The recommended bypass capacitor values for the VCCIRO pin are 2.2 F or 4.7 F X7R, and 470 pF or 1 nF NPO type. These capacitors will help filter out noise at the output of the internal voltage regulator, which is important for the ATF1508RE to operate properly (see Figure 2-3). The ATF1508RE CPLD also supports MultiVolt I/O interface feature, which allows seamless interface to other devices at 1.5V, 1.8V, 2.5V, or 3.3V logic levels. The ATF1508RE device has two I/O banks, each bank can be supplied with an independent VCCIO (VCCIOA or VCCIOB). Figure 2-3. On-Chip Voltage Regulator ATF1508RE Core Logic 1.8V Internal Voltage Regulator VCCIRI = 3.3V Pin 91 for 100 TQFP VCCIRO = 1.8V Pin 39 for 100 TQFP 470 pF or 1 nF 2.2 F or 4.7 F 3. Power Management Unlike conventional CPLDs with sense amplifiers, the ATF1508RE is designed using low-power full CMOS design techniques. This enables the ATF1508RE to achieve extremely low power consumption over the full operating frequency spectrum. The ATF1508RE also has an optional power-down mode. In this mode, current drops to below 100 A. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. When enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin's macrocell may still be used to generate buried foldback and cascade logic signals. All power-down AC characteristic parameters are computed from external input or I/O pins. 4. Security Feature A fuse is provided to prevent unauthorized copying of the ATF1508RE fuse patterns. Once enabled, fuse reading or verification is inhibited. However, the 16-bit User Electronic Signature remains accessible. To reset this feature, the entire memory array in the device must be erased. 10 ATF1508RE 3682A-PLD-10/08 ATF1508RE 5. Programming Methods The ATF1508RE devices are In-System Programmable (ISP) or In-System Configurable (ISC) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. When using the ISP hardware or software to program the ATF1508RE devices, four I/O pins must be reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O pins are still available to the design for buried logic functions. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by Atmel-provided software utilities. ATF1508RE devices can also be programmed using standard third-party programmers. With a third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic. The ATF1508RE device supports several configuration modes which gives designers several unique options for programming. The different modes of programming are: * ISC - In-System Configuration * OTF - On-the-Fly Reconfiguration * DRA - Direct Reconfiguration Access 5.1 In-System Configuration - ISC (Also Referred to as ISP) This mode is the de-facto standard used to program the CPLD when it is attached to a PCB. The term ISC can also be used interchangeably with ISP (In-system Programming). ISC or ISP eliminates the need for an external device programmer, and the devices can be soldered to a PCB without being preprogrammed. In the ISC mode, the logic operation of the ATF1508RE is halted and the embedded configuration memory is programmed. The device is programmed by first erasing the configuration memory in the CPLD and then loading the new configuration data into the memory, which in-turn configures the PLD for functional mode. When the device is in the ISC programming mode, all user I/Os are held in the high impedance state. The ISC mode is best suited for working with the ATF1508RE device in a design development or production environment. Configuration of the ATF1508RE device done via a Download Cable (see Figure 5-1 on page 11) is the default mode used to program the device in the ISC mode. In this mode, the PC is typically the controlling device that communicates with the CPLD. Figure 5-1. Configuration of ATF1508RE Device Using a Download Cable ATF1508RE CPLD Device TCK TDO 1 3 2 4 6 8 10 Connect ISP Download Cable to 10-pin JTAG Header VCC TMS TDI 5 7 9 JTAG Connector 11 3682A-PLD-10/08 5.2 On-the-Fly Reconfiguration - OTF In this mode, the CPLD design pattern stored in the internal configuration memory can be modified while the previously-programmed design pattern is operating with minimal disturbance to the programming operation of the new design. The new configuration will take affect after the OTF programming process is completed and the OTF mode is exited. The configuration data for any design is stored in the internal configuration memory. Once the configuration data is transferred to the internal static registers of the CPLD, the CPLD operates with the design pattern and the configuration memory is free to be re-loaded with a new set of configuration data. The design pattern due to the new configuration content is activated through an initialization cycle that occurs on exiting the OTF mode or after the next power up sequence. Figure 5-2 shows the electrical interface for configuration of the ATF1508RE device in the OTF mode. The processor is the controlling device that communicates with the CPLD and uses configuration data stored in the external memory to configure the CPLD. Figure 5-2. Configuration of ATF1508RE Device Using a Processor and Memory ATF1508RE CPLD Device TCK TDO Processor TMS TDI Serial Data Data Address Memory 5.3 Direct Reconfiguration Access - DRA This reconfiguration mode allows the user to directly modify the internal static registers of the CPLD without affecting the configuration data stored in the embedded memory. It is more useful in cases where immediate and temporary context change in the function of the hardware is desired. The embedded configuration memory in the ATF1508RE does not change when a new set of configuration data is passed to the ATF1508RE using the DRA mode. Instead, the internal static registers of the CPLD are directly written with the data entering the device via the JTAG port. In other words, it's a temporary change in the function performed by the CPLD since a power sequence results in the device being configured again by the data stored in the embedded memory. 5.4 ISP Programming Protection The ATF1508RE has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The I/O pins default to high-Z state during such a condition. All ATF1508RE devices are initially shipped in the erased state, thereby making them ready to use for ISP. 12 ATF1508RE 3682A-PLD-10/08 ATF1508RE 6. JTAG-BST/ISP Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1508RE. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing methods. Each input pin and I/O pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1508RE's BSC can be fully described using a BSDL file as described in IEEE 1149.1 standard. This allows ATF1508RE testing to be described and implemented using any one of the third-party development tools supporting this standard. The ATF1508RE also has the option of using the four JTAG-standard I/O pins for ISP. The ATF1508RE is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE 1532 standard using 1.8V/2.5V/3.3V LVCMOS level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. 6.1 JTAG Boundary-scan Cell (BSC) Testing The ATF1508RE contains 80 I/O pins and four dedicated input pins. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE 1532 standard. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown below. Figure 6-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: The ATF1508RE has a pull-up option on TMS and TDI pins. This feature is selected as a design option. 13 3682A-PLD-10/08 Figure 6-2. BSC Configuration for Macrocell TDO QD 0 1 CLOCK TDI TDO OEJ 0 0 1 1 DQ DQ OUTJ 0 0 1 Capture DR Update DR 1 DQ DQ Pin TDI Shift Clock Mode BSC for I/O Pins and Macrocells 7. Design Software Support ATF1508RE designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages such as VHDL(R) and Verilog(R). Third party synthesis and simulation tools from Mentor Graphics(R) are integrated into Atmel's software tools. 8. Electrical Specifications Table 8-1. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature...................................-40 C to +85 C Storage Temperature ....................................-65 C to +150 C Supply Voltage (VCCINT) .................................... -0.5V to +2.5V Supply Voltage for Output Drivers (VCCIO) ........ -0.5V to +4.5V Junction Temperature ...................................-55 C to +155 C 14 ATF1508RE 3682A-PLD-10/08 ATF1508RE Table 8-2. Operating Temperature Range Commercial Industrial -40 C - 85 C Operating Temperature (Ambient) 0 C - 70 C Table 8-3. Pin Capacitance(1) Typ Max 10 10 Units pF pF Conditions VIN = 0V; f = 1.0 MHz VOUT = 0V; f = 1.0 MHz CIN CI/O Note: 8 8 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 15 3682A-PLD-10/08 Table 8-4. Symbol VCCIRI VCCIO VCCIO VCCIO VCCIO ISB_IO ISB_INT ICC_INT(HD) DC Characteristics Parameter Supply Voltage for internal logic and input buffers Supply Voltage for output drivers at 3.3V Supply Voltage for output drivers at 2.5V Supply Voltage for output drivers at 1.8V Supply Voltage for Output Drivers at 1.5V Standby Current, VCCIO Standby Current, VCC Core Operating Current for VCCIRI (supply voltage) Operating Current(1) for VCCIO (supply voltage for output drivers), per LAB Operating Current(1) for VCCIRI (low drive) Operating Current(1) for VCCIO (supply voltage for output drivers), per LAB Input Leakage Output or IO Leakage (1) (1) Condition Min 3.0 3.0 2.3 1.7 1.4 Typ 3.3 3.3 2.5 1.8 1.5 1 130 450 Max 3.6 3.6 2.7 1.9 1.6 Units V V V V V A A A VCCIO = 3.3V, VCCIRI = 3.3V VCCIRI = 3.3V, VCCIO = 3.3V VCCIRI = 3.3V, VCCIO = 3.3V, f = 1 MHz VCCIRI = 3.3V, VCCIO = 3.3V, f = 1 MHz VCCIRI = 3.3V, VCCIO = 3.3V, f = 1 MHz VCCIRI = 3.3V, VCCIO = 3.3V, f = 1 MHz VCCIRI = 3.3V, VIN = 0V or 1.9V VCCIRI = 3.3V, VCCIRO = 3.6V, VIN = 0V or VCCIRO ICC_IO(HD) 375 A ICC_INT(LD) 450 A ICC_IO(LD) IIL, IIH IOZH, IOH 150 1 1 A A A LVCMOS 3.3V & LVTTL (HD: High Drive, LD: Low Drive) VIL VIH VOL Input Low-voltage Input High-voltage Output Low-voltage HD: IOL = 8 mA, VCCIO = 3V LD: IOL = 1 mA, VCCIO = 3V Output High-voltage HD: IOH = -8 mA, VCCIO = 3V LD: IOH = -1 mA, VCCIO = 3V VCCIO - 0.4V VCCIO - 0.4V -0.3 2 0.8 3.9 0.4 0.4 V V V V V V VOH LVCMOS 2.5V VIL VIH VOL Input Low-voltage Input High-voltage Output Low-voltage HD: IOL = 8 mA, VCCIO = 2.3V LD: IOL = 1 mA, VCCIO = 2.3V Output High-voltage HD: IOH = -8 mA, VCCIO = 2.3V LD: IOH = -1 mA, VCCIO = 2.3V VCCIO - 0.4V VCCIO - 0.4V -0.3 1.7 0.7 3.9 0.4 0.4 V V V V V V VOH 16 ATF1508RE 3682A-PLD-10/08 ATF1508RE Table 8-4. Symbol DC Characteristics (Continued) Parameter Condition Min Typ Max Units LVCMOS 1.8V VIL VIH VOL Input Low-voltage Input High-voltage Output Low-voltage HD: IOL = 2 mA, VCCIO = 1.7V LD: IOL = 1 mA, VCCIO = 1.7V Output High-voltage HD: IOH = -2 mA, VCCIO = 1.7V LD: IOH = -1 mA, VCCIO = 1.7V VCCIO - 0.45V VCCIO - 0.45V -0.3 1.2 0.35 x VCCIO 3.9 0.45 0.2 V V V V V V VOH LVCMOS 1.5V VIL VIH VOL Input Low-voltage Input High-voltage Output Low-voltage HD: IOL = 2 mA, VCCIO = 1.4V LD: IOL = 1 mA, VCCIO = 1.4V Output High-voltage HD: IOH = -2 mA, VCCIO = 1.4V LD: IOH = -1 mA, VCCIO = 1.4V 1. 16-bit up/down counter used in each LAB. VCCIO - 0.45V VCCIO - 0.45V -0.3 1.2 0.35 x VCCIO 3.9 0.45 0.2 V V V V V V VOH Note: Table 8-5. Schmitt Trigger Input Threshold Voltage VTHL VTLH Max 0.73 0.88 Min 1.05 1.18 Max 1.08 1.22 VCCIRI 3.0V 3.6V Min 0.68 0.81 Table 8-6. Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL VIH(DC) VIL(DC) Notes: SSTL2-1 DC Voltage Specifications Parameter Input Source Voltage Input Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage IOH = -8 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V VREF + 0.15 -0.3 Conditions Min 2.3 1.15 VREF - 0.05 VREF + 0.45 -0.3 VCCIO - 0.6 0.54 VCCIO + 0.3 VREF - 0.15 Typ 2.5 1.25 1.25 Max 2.7 1.35 VREF + 0.04 3.9 VREF - 0.6 Units V V V V V V V V V 1. Peak-to-peak noise on VREF may not exceed 2% VREF, VREF should track the variations in VCCIO. 2. VTT of transmitting device must track VREF of receiving devices. 17 3682A-PLD-10/08 Table 8-7. Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL VIH(DC) VIL(DC) Notes: SSTL3-1 DC Voltage Specifications Parameter Input Source Voltage Input Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage IOH = -8 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 2.3V VREF + 0.18 -0.3 Conditions Min 3.0 1.3 VREF - 0.05 VREF + 0.4 -0.3 VCCIO - 1.1 0.7 VCCIO + 0.3 VREF - 0.18 Typ 3.3 1.5 1.5 Max 3.6 1.7 VREF + 0.05 VCCIO + 0.3 VREF - 0.6 Units V V V V V V V V V 1. Peak-to-peak noise on VREF may not exceed 2% VREF, VREF should track the variations in VCCIO. 2. VTT of transmitting device must track VREF of receiving devices. 9. Timing Model Internal Output Enable Delay tIOE Input Delay tIN (+tSCH) Global Control Delay tGLOB Switch Matrix tUIM Logic Array Delay tLAD Register Control Delay tLAC tIC tEN Foldback Term Delay tSEXP Cascade Logic Delay tPEXP Fast Input Delay tFIN Register/ Combinatorial Delays tSUI tHI tPRE tCLR tRD tCOMB tFSUI tFHI Output Delay tOD1 (+tSSO) tXZ tZX1 tZX2 (+SSTL2-1_OAD) (+SSTL3-1_OAD) I/O Delay tIO (+tSCH) (+SSTL2-1_IAD) (+SSTL3-1_IAD) 18 ATF1508RE 3682A-PLD-10/08 ATF1508RE 10. Output AC Test Loads VCCIO Device Under Test R1 Test Point R2 CL R1 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 Note: 350 Ohm 300 Ohm 200 Ohm 150 Ohm R2 350 Ohm 300 Ohm 200 Ohm 150 Ohm CL 35 pF 35 pF 35 pF 35 pF CL includes test fixtures and probe capacitance. 19 3682A-PLD-10/08 11. AC Characteristics Table 11-1. AC Characteristics (1) -5 Symbol tPD1_INP tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT tACNT fACNT fMAX_EXT_SYNC fMAX_EXT_ASYNC tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE Parameter Delay for Single Input to Non-registered Output Input or Feedback to Non-registered Output Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold Time of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock to Output Delay Array Clock High Time Array Clock Low Time Minimum Global Clock Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum External Frequency Maximum External Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay VCCIO = 1.5V VCCIO = 1.8V VCCIO = 2.5V VCCIO = 3.3V VCCIO = 3.3V VCCIO = 3.3V 0.7 0.7 1 2 0.5 1.8 1.5 2 4.5 4.0 3.5 2.8 250 122 122 333 4 181 103 103 0.9 0.9 1 3 1.0 1.8 2 2 4.5 4.0 3.5 2.8 1.75 1.75 3 210 5.5 1.25 1.25 1.7 0.50 6.5 2.5 2.5 4.75 2.2 0 1 0.5 6 2 2 2.2 0.60 7.5 Min Max 5.0 7 4.2 2.8 0 2 0.75 6.9 Min -7 Max 6 7.5 4.7 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz MHz ns ns ns ns ns ns ns ns tOD1 Output Buffer Delay (HD) (High Drive; CL = 35 pF) ns 20 ATF1508RE 3682A-PLD-10/08 ATF1508RE Table 11-1. AC Characteristics (Continued)(1) -5 Symbol Parameter VCCIO = 1.5V VCCIO = 1.8V VCCIO = 2.5V VCCIO = 3.3V VCCIO = 1.5V VCCIO = 1.8V VCCIO = 2.5V VCCIO = 3.3V Min Max 5.0 4.5 3.5 3.0 6.0 5.5 4.5 4.0 4 1.7 0.5 0.5 0.5 0.7 1.2 1.8 2.5 1.8 1.75 1.75 0.5 1.5 VCCIO = 1.5V VCCIO = 1.8V VCCIO = 2.5V VCCIO = 3.3V VCCIO = 2.5V VCCIO = 3.3V VCCIO = 2.5V VCCIO = 3.3V 6.5 5.5 5.25 5 1.5 1.5 1 1 2.2 0.6 0.6 0.6 1.2 1.2 1.8 3 2 2 2 0.8 2 8.5 7.5 7.25 7 1.5 1.5 1 1 Min -7 Max 6.0 5.5 4.5 4.0 7.0 6.5 5.5 5.0 4 Units tZX1 Output Buffer Enable Delay (High Drive; CL = 35 pF) ns tZX2 Output Buffer Enable Delay (Low Drive; CL = 35 pF) Output Buffer Disable Delay (CL = 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay Schmitt Trigger Added Delay ns tXZ tSUI tHI tFSUI tFHI tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tSCH ns ns ns ns ns ns ns ns ns ns ns ns ns ns tSSO Output Added Delay for VCCIO Level (LD) ns SSTL2-1_IAD(2) SSTL3-1_IAD(2) SSTL2-1_OAD(2) SSTL3-1_OAD(2) Note: SSTL Input Delay Adder (HD) SSTL Output Delay Adder (HD) ns ns 1. See ordering information for valid part numbers. 2. SSTL is not supported for low drive output (LD). 21 3682A-PLD-10/08 12. Power-down Mode The ATF1508RE includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 100 A. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The powerdown pin feature is enabled in the logic design file or through Atmel software. Designs using the power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. Table 12-1. Power-down AC Characteristics(1)(2) -5/-7 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes: Parameter Valid I, I/O before PD High Valid OE (2) Min 10 10 10 Max Units ns ns ns before PD High (2) Valid Clock before PD High I, I/O Don't Care after PD High OE (2) 5 5 5 2 2 2 2 ns ns ns s s s s Don't Care after PD High (2) Clock Don't Care after PD High PD Low to Valid I, I/O PD Low to Valid OE (Pin or Term) PD Low to Valid Clock (Pin or Term) PD Low to Valid Output 1. For low-drive outputs, add tSSO. 2. Pin or product term. 22 ATF1508RE 3682A-PLD-10/08 ATF1508RE 13. ATF1508RE Dedicated Pinouts Table 13-1. ATF1508RE Dedicated Pinouts 132-ball CBGA C3 A3 C2 L2 M8 F1, G12 H1 L13 M9 N10 M10 B9 A9, B14, B3, E14, H14, J14, K2, N1, N9, N12, P4 K12, A2 P1 J3, P7, P13, G14 A7, A14, C4 L1, L3, M1, N4, C13, B10, D3, P6, P8, N2, N7, N8, M7, M2, M12, M13, M14, C7, C8, C14, B6, B7, B8, B13, A6, A8, A13 84 80 84 80 100-lead TQFP 90 89 88 87 85 1, 41 12 60 4 15 62 73 11, 26, 38, 43, 59, 74, 86, 95 91 39 3, 18, 34 51, 66, 82 Dedicated Pin INPUT / OE2 / GCLK2 INPUT / GCLR INPUT / OE1 INPUT / GCLK1 I/O / GCLK3 I/O / PD (1,2) I/O / VREFA I/O / VREFB I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND VCCIRI VCCIRO VCCIOA VCCIOB N/C # of Signal Pins # User I/O Pins OE (1, 2) GCLR GCLK (1, 2, 3) PD (1, 2) TDI, TMS, TCK, TDO GND VCCIRI VCCIOA VCCIOB VREFA VREFB VCCIRO Global OE pins Global Clear pin Global Clock pins Power-down pins JTAG pins used for boundary-scan testing or in-system programming Ground pins Core VCC input pin for the device regulator (+3.0V - 3.6V) LAB A and B - VCC supply pins for I/Os (1.5V, 1.8V, 2.5V, or 3.3V) LAB C and D - VCC supply pins for I/Os (1.5V, 1.8V, 2.5V, or 3.3V) Reference voltage pin for SSTL inputs in bank A Reference voltage pin for SSTL inputs in bank B Output pin of the regulator to be used for capacitor coupling only. 23 3682A-PLD-10/08 Table 13-2. MC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ATF1508RE I/O Pinouts Logic Block A A A/ PD1 A A A A A A A A A A A A A B B B B B/VREFA B B B B B B B B B B B/ TDI 100-lead TQFP 2 1 100 99 98 97 96 94 93 92 14 13 12 10 9 8 7 6 5 4 132-ball CBGA G1 F1 F2 F3 E1 E2 E3 D1 D2 C1 C2 G3 H1 H2 H3 J1 J2 K1 K3 M9 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Logic Block C C C C C C C C C C C C C C C C/ TMS D D D D D D D D D D D D D D D D 100-lead TQFP 25 24 23 22 21 20 19 17 16 15 37 36 35 33 32 31 30 29 28 27 132-ball CBGA B1 B2 A1 B4 A4 C5 B5 A5 C6 N10 P2 M3 N3 P3 M4 M5 N5 P5 M6 N6 24 ATF1508RE 3682A-PLD-10/08 ATF1508RE Table 13-2. MC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ATF1508RE I/O Pinouts (Continued) Logic Block E E E/ PD2 E E E E E E E E E E E E E F F F F F F F F F F F F F/VREFB F F F/ TCK 100-lead TQFP 40 41 42 44 45 46 47 48 49 50 52 53 54 55 56 57 58 60 61 62 132-ball CBGA G13 G12 F14 F13 F12 E13 E12 D14 D13 D12 H12 H13 J13 J12 K14 K13 L14 L13 L12 M10 MC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Logic Block G G G G G G G G G G G G G G G G/ TDO H H H H H H H H H H H H H H H H/ GCLK3 100-lead TQFP 63 64 65 67 68 69 70 71 72 73 75 76 77 78 79 80 81 83 84 85 132-ball CBGA C12 B12 A12 C11 B11 A11 C10 A10 C9 B9 N14 N13 P14 P12 M11 N11 P11 P10 P9 M8 25 3682A-PLD-10/08 14. Typical DC and AC Characteristic Graphs ICC INT & ICC I/O (HD) @ VCCIRI = 3.3V Over Frequency, Room Temp 800 35 30 ICC INT & ICC I/O (HD) @ VCCIRI = 3.3V Over Frequency, Room Temp 600 400 200 Freq. (MHz) Iccio_Vccio_1.5V Iccio_Vccio_1.8V Iccio_Vccio_2.5V Iccio_Vccio_3.3V Iccint_Vccio_3.3V 25 ICC (uA) 20 15 10 5 0 1 2 5 10 20 50 100 Iccio_Vccio_1.5V Iccio_Vccio_1.8V Iccio_Vccio_2.5V Iccio_Vccio_3.3V Iccint_Vccio_3.3V 0 0 0.025 0.1 0.2 Frequency (MHz) 0.5 1 2 ICC (mA) Frequency (MHz) ICC INT & ICC I/O (LD) @ VCCIRI = 3.3V Over Frequency, Room Temp 800 35 30 ICC INT & ICC I/O (LD) @ VCCIRI = 3.3V Over Frequency, Room Temp 600 400 Iccio_Vccio_1.5V Iccio_Vccio_1.8V Iccio_Vccio_2.5V Iccio_Vccio_3.3V Iccint_Vccio_3.3V 25 ICC (mA) 20 15 10 5 200 Iccio_Vccio_1.5V Iccio_Vccio_1.8V Iccio_Vccio_2.5V Iccio_Vccio_3.3V Iccint_Vccio_3.3V ICC (uA) 0 0 0.025 0.1 0.2 Frequency (MHz) 0.5 1 2 0 1 2 5 10 Frequency (MHz) 20 50 100 OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE (VCCIRI = 3.3V, VCCIO = 1.5-3.3V, TA = 25C), High Drive 160 0 -20 OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE (VCCIRI = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), High Drive 120 IOH ( mA ) IOL ( mA ) 1.5V 80 1.8V 2.5V 3.3V 40 -40 -60 -80 -100 1.5V 1.8V 2.5V 3.3V 0 0. 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 1. 8 2. 0 2. 2 2. 4 2. 6 2. 8 3. 0 3. 2 3. 4 -120 0. 0 0. 8 1. 8 1. 2 1. 4 1. 6 2. 0 2. 2 2. 4 2. 6 2. 8 3. 0 0. 4 0. 6 0. 2 1. 0 3. 2 OUTPUT VOLTAGE ( V ) OUTPUT VOLTAGE ( V ) 26 ATF1508RE 3682A-PLD-10/08 ATF1508RE OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE (VCCIRI = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), Low Drive 25 OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE (VCCIRI = 1.8V, VCCIO =1.5-3.3V, TA = 25C), Low Drive 0 20 1.5V 1.8V 2.5V 10 3.3V -5 1.5V 1.8V 2.5V -15 3.3V IOL ( mA ) 5 IOH ( mA ) 15 -10 -20 0 0. 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 1. 8 2. 0 2. 2 2. 4 2. 6 2. 8 3. 0 3. 2 3. 4 -25 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT VOLTAGE ( V ) OUTPUT VOLTAGE ( V ) INPUT CURRENT VS. INPUT VOLTAGE INPUT PIN (VCCIRI = 3.3V, TA = 25C) (PIN-KEEPER ON) 80 60 INPUT CURRENT ( uA ) 0.0 -5.0 INPUT CURRENTN (A) -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 INPUT & I/O CURRENT VS. INPUT VOLTAGE VCCIRI = 3.3V, VCCIO = 1.8V (TA = 25C) (Pull-Up On) 40 20 0 -20 -40 -40.0 4 0 6 0 2 6 8 2 4 8 0 2 4 6 8 0 0.5 1 INPUT VOLTAGE (V) 1.5 3.2 1.8 0. 1. 1. 2. 0. 0. 0. 0. 1. 1. 1. 2. 2. 2. INPUT VOLTAGE ( V ) I/O PIN CURRENT VS. I/O PIN VOLTAGE I/O PIN (VCCIRI = 3.3V, VCCIO = 1.5V-3.3V, TA = 25C) (PIN KEEPER ON) 200 150 I/O PIN CURRENT ( uA ) TPD (ns) 2. TPD VS. # MC SWITCHING (VCCIRI = 3.3V, VCCIO = 1.5-3.3V, TA = 25C) 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 4.8 1. 0 4. 0 8. 0 16 .0 32 .0 60 .0 100 1.5V 50 0 -50 -100 -150 0. 0 0. 4 1. 2 0. 8 1. 6 2. 0 2. 4 3. 2 2. 8 3. 6 4. 0 4. 8 4. 4 1.5V 1.8V 2.5V 3.3V 1.8V 2.5V 3.3V I/O PIN VOLTAGE ( V ) # MC SWITCHING 27 3682A-PLD-10/08 15. Ordering Information 15.1 tPD (ns) 5 7 5 7 Note: Lead-free Package Options (RoHS Compliant) tCO (ns) 6 6.5 6 6.5 Ordering Code ATF1508RE-5AX100 ATF1508RE-7AU100 ATF1508RE-5CX132 ATF1508RE-7CU132 Package 100A 100A 132C1 132C1 Operation Range Commercial (0 C to +70 C) Industrial (-40 C to +85 C) Commercial (0 C to +70 C) Industrial (-40 C to +85 C) For shaded devices, contact marketing for availability. Package Type 100A 132C1 100-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 132-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 28 ATF1508RE 3682A-PLD-10/08 ATF1508RE 16. Packaging Information 16.1 100A - TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.50 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. 2. 3. This package conforms to JEDEC reference MS-026, Variation AED. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is 0.08 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. C R 29 3682A-PLD-10/08 17. Revision History Revision Level - Release Date A - October 2008 History Initial release 30 ATF1508RE 3682A-PLD-10/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support pld@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, Everywhere You Are (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Mentor Graphics (R) is the registered trademark of Mentor Graphics (R) (R) Corporation. Verilog is the registered trademarks of Cadence Design Systems, Inc. VHDL is the trademark of Synopsys, Inc. Other terms and product names may be trademarks of others. 3682A-PLD-10/08 |
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